- 目錄
第1篇 后端設計工程師崗位職責
ic后端設計工程師 南京華捷艾米 南京華捷艾米軟件科技有限公司,華捷艾米,南京華捷艾米,南京華捷艾米 responsibilities:
responsible for all aspects of chip backend design, including floor planning, place and routing, cts, timing convergence iterations/optimization, and final drc/lvs.
qualifications:
1. bsee, msee or higher.
2. at least 2 years experience of large asic backend designs.
3. experience with synopsys and/or cadence design tools.
4. have 65/40/28nm experience is better.
5. good communication skills, team spirit.
工作職責:
負責整個芯片或模塊的布局布線設計, 包括布局規(guī)劃, 布局布線, 時鐘樹生成, 時序優(yōu)化和收斂, 以及 drc/lvs物理驗證.
任職資格:
1. 電子工程或微電子專業(yè)本科及以上學歷;
2. 至少2年以上大規(guī)模集成電路芯片后端設計經(jīng)驗;
3. 具有使用synopsys 或cadence 設計工具的相關經(jīng)驗;
4. 最好有65/40/28nm設計經(jīng)驗;
5. 良好溝通能力和團隊精神。
第2篇 ic后端設計工程師崗位職責
ic后端設計工程師 南京華捷艾米 南京華捷艾米軟件科技有限公司,華捷艾米,南京華捷艾米,南京華捷艾米 responsibilities:
responsible for all aspects of chip backend design, including floor planning, place and routing, cts, timing convergence iterations/optimization, and final drc/lvs.
qualifications:
1. bsee, msee or higher.
2. at least 2 years experience of large asic backend designs.
3. experience with synopsys and/or cadence design tools.
4. have 65/40/28nm experience is better.
5. good communication skills, team spirit.
工作職責:
負責整個芯片或模塊的布局布線設計, 包括布局規(guī)劃, 布局布線, 時鐘樹生成, 時序優(yōu)化和收斂, 以及 drc/lvs物理驗證.
任職資格:
1. 電子工程或微電子專業(yè)本科及以上學歷;
2. 至少2年以上大規(guī)模集成電路芯片后端設計經(jīng)驗;
3. 具有使用synopsys 或cadence 設計工具的相關經(jīng)驗;
4. 最好有65/40/28nm設計經(jīng)驗;
5. 良好溝通能力和團隊精神。
第3篇 數(shù)字后端設計工程師崗位職責
數(shù)字后端設計工程師 西安紫光國芯半導體有限公司 西安紫光國芯半導體有限公司,華芯半導體,西安紫光國芯,西安紫光國芯半導體有限公司,紫光國芯 asic backend design engineer (be)
數(shù)字后端設計工程師
responsibilities:
1. responsible for developing digital designs with emphasis on backend, including floor-plan, power planning, place, cts and route.
2. work with front-end designers to optimize timing/area/power of the design implementation and perform static timing analysis.
3. optimization and verification of layout for tape-out (including rc extraction, eco, drc, lvs).
4. power ir drop analysis and optimization, area and parasitic layout optimization, chip size optimization.
5. static timing analysis (prime time) and setup/hold fix.
6. formal verification for equivalence checking (formality).
7. generation of fill structures according to technology requirements.
requirements:
1. 4 years experience in backend design flow (apr) with proven soc tape-out experience.
2. experienced in synopsys/cadence automatically physical implementation tools and flows (ic-compiler/ astro / soc-encounter/ milky-way/ star-rcx) is a plus.
3. experience with one or more scripting languages (perl, tcl, or shell) to make reusable automatically flow is a plus.
4. experience and knowledge about fe design (rtl code, flow) and verification is a plus.
5. good analytical and debugging skills.
6. good command of english.
第4篇 芯片后端設計工程師崗位職責
工作職責
負責asic/soc芯片的物理實現(xiàn)及推動項目按時保質完成,主要包括:主導floorplan,placement&routing,power planning,physical verification, top & block level timing closure; function and timing eco等方面的具體實現(xiàn)工作;負責與前端設計團隊、foundry/design service/test&package/ip vendor的溝通,并推動所有問題按時解決;負責推動項目的后端整體進度,并順利投片。
工作要求
一本全日制本科或碩士畢業(yè),從事芯片物理設計3年以上, 熟悉rtl設計和驗證基本流程;熟悉lint和cdc相關工具; 熟悉物理設計流程;具有豐富的頂層floorplan經(jīng)驗;具有豐富的placement&routing經(jīng)驗;具有l(wèi)ow power, dft, sta, em/ir-drop/si analysis, lec, physical verification, dfm等方面扎實的理論和實踐基礎;具有28nm以下工藝節(jié)點流片經(jīng)驗者優(yōu)先。
